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| 512 x 18, 1k x 18, and 2k x 18 cascadable clocked fifos with programmable flags cy7c455 cy7c456 CY7C457 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 october 1992 - revised januar y 3 , 1997 features ? high-speed, low-power, first-in first-out (fifo) memories ? 512 x 18 (cy7c455) ? 1,024 x 18 (cy7c456) ? 2,048 x 18 (CY7C457) ? 0.65 micron cmos for optimum speed/power ? high-speed 83-mhz operation (12 ns read/write cycle time) ? low power i cc =90 ma ? fully asynchronous and simultaneous read and write operation ? empty, full, half full, and programmable almost empty and almost full status flags ? ttl compatible ? retransmit function ? parity generation/checking ? output enable (oe ) pins ? independent read and write enable pins ? center power and ground pins for reduced noise ? supports free-running 50% duty cycle clock inputs ? width expansion capability ? depth expansion capability ? 52-pin plcc and 52-pin pqfp functional description the cy7c455, cy7c456, and CY7C457 are high-speed, low-power, first-in first-out (fifo) memories with clocked read and write interfaces. all are 18 bits wide. the cy7c455 has a 512-word memory array, the cy7c456 has a 1,024-word memory array, and the CY7C457 has a 2,048-word memory array. the cy7c455, cy7c456, and CY7C457 can be cas- caded to increase fifo depth. programmable features include almost full/empty flags and generation/checking of parity. these fifos provide solutions for a wide variety of data buff- ering needs, including high-speed data acquisition, multipro- cessor interfaces, and communications buffering. these fifos have 18-bit input and output ports that are con- trolled by separate clock and enable signals. the input port is controlled by a free-running clock (ckw) and a write enable pin (enw ). logic block diagram pin configurations c455-1 c455-2 parity threeCstate output register read control flag logic write control write pointer read pointer reset logic expansion logic input register flag/parity program register d 0C 17 enr ckr hf e /f pafe /xo q 0C 7 ,q 8 /pg1/pe1 q 9C 16 , q17/pg2/pe2 enw ckw mr fl/rt xi oe ram array 512 x 18 1024 x 18 2048 x 18 1 top view plcc 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 5251504948 47 e /f enw xo /pafe hf d 2 d 1 d 0 xi ckw q 0 q 1 q 2 q 3 d 13 d 14 d 15 d 16 d 17 fl/rt mr ckr enr oe q 17 q 16 q 15 d 12 d 11 d 10 d 9 v cc (n) v cc v ss d 8 d 7 d 6 d 5 d 4 d 3 q 4 q 5 q 6 q 7 q 8 /pg1/pe1 v ss v ss (n) q 9 q 10 q 11 q 12 q 13 q 14 retransmit logic /pg2/pe2 7c455 7c456 7c457
cy7c455 cy7c456 CY7C457 2 functional description (continued) in the standalone and width expansion configurations, a low on the retransmit (rt ) input causes the fifos to retransmit the data. read enable (enr ) and the write enable (enw ) must both be high during the retransmit, and then enr is used to access the data.when enw is asserted, data is written into the fifo on the rising edge of the ckw signal. while enw is held active, data is continually written into the fifo on each ckw cycle. the output port is controlled in a similar manner by a free-running read clock (ckr) and a read enable pin (enr ). in addition, the cy7c455, cy7c456, and CY7C457 have an output enable pin (oe ). the read (ckr) and write (ckw) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. clock frequencies up to 83.3 mhz are achievable in the standalone configuration, and up to 83.3 mhz is achievable when fifos are cascaded for depth expan- sion. depth expansion is possible using the cascade input (xi ), cas- cade output (xo ), and first load (fl ) pins. the xo pin is connected to the xi pin of the next device, and the xo pin of the last device should be connected to the xi pin of the first device. the fl pin of the first device is tied to v ss . the cy7c455, cy7c456, and CY7C457 provide three status pins. these pins are decoded to determine one of six states: empty, almost empty, less than or equal to half full, greater than half full, almost full, and full (see ta ble 1 ). the almost empty/full flag (pafe ) shares the xo pin on the cy7c455, cy7c456, and CY7C457. this flag is valid in the standalone and width-expansion configurations. in the depth expansion, this pin provides the expansion out (xo ) information that is used to signal the next fifo when it will be activated. the flags are synchronous, i.e., they change state relative to either the read clock (ckr) or the write clock (ckw). when entering or exiting the empty and almost empty states, the flags are updated exclusively by the ckr. the flags denoting half full, almost full, and full states are updated exclusively by ckw. the synchronous flag architecture guarantees that the flags maintain their status for some minimum time. this time is typically equal to approximately one cycle time. the cy7c455/6/7 uses center power and ground for reduced noise. all configurations are fabricated using an advanced 0.65u cmos technology. input esd protection is greater than 2001v, and latch-up is prevented by the use of guard rings. pin configurations (continued) 46 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 45 44 43 42 41 40 e /f enw xo /pafe hf d 2 d 1 d 0 xi ckw q 0 q 1 q 2 q 3 d 12 d 11 d 10 d 9 v cc (n) v cc v ss d 8 d 7 d 6 d 5 d 4 d 3 d 13 d 14 d 15 d 16 d 17 fl/rt mr ckr enr oe q 17 /pg2/pe2 q 16 q 15 c455-3 top view pqfp q 4 q 5 q 6 q 7 q 8 /pg1/pe1 v ss v ss (n) q 9 q 10 q 11 q 12 q 13 q 14 7c455 7c456 7c457 cy7c455 cy7c456 CY7C457 3 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................C65 c to +150 c ambient temperature with power applied ............................................C55 c to +125 c supply voltage to ground potential ............... C0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... C0.5v to +7.0v dc input voltage ............................................ C3.0v to +7.0v output current into outputs (low) ............................. 20 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma selection guide 7c455/6/7C12 7c455/6/7C14 7c455/6/7C20 7c455/6/7C30 maximum frequency (mhz) 83.3 71.4 50 33.3 maximum cascadable frequency 83.3 71.4 50 33.3 maximum access time (ns) 9 10 15 20 minimum cycle time (ns) 12 14 20 30 minimum clock high time (ns) 5 6.5 9 12 minimum clock low time (ns) 5 6.5 9 12 minimum data or enable set-up (ns) 4 5 6 7 minimum data or enable hold (ns) 0 0 0 0 maximum flag delay (ns) 9 10 15 20 maximum current (ma) commercial 160 160 140 120 industrial 180 180 160 140 selection guide (continued) cy7c455 cy7c456 CY7C457 density 512 x 18 1,024 x 18 2,048 x 18 oe , depth cascadable ye s ye s ye s package 52-pin plcc/pqfp 52-pin plcc/pqfp 52-pin plcc/pqfp operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial [1] C40 c to +85 c 5v 10% note: 1. t a is the instant on case temperature. cy7c455 cy7c456 CY7C457 4 pin definitions signal name i/o description d 0 - 17 i data inputs: when the fifo is not full and enw is active, ckw (rising edge) writes data (d 0 - 17 ) into the fifos memory. if mr is asserted at the rising edge of ckw, data is written into the fifos programming register. d 8 , 17 are ignored if the device is configured for parity generation. q 0 - 7 q 9 - 16 o data outputs: when the fifo is not empty and enr is active, ckr (rising edge) reads data (q 0 - 7 , q 9 - 16 ) out of the fifos memory. if mr is active at the rising edge of ckr, data is read from the programming register. q 8 /pg1/pe1 q 17 /pg2/pe2 o function varies according to mode: parity disabled C same function as q 0 - 7 and q 9 - 16 parity enabled, generation C parity generation bit (pg x ) parity enabled, check C parity error flag (pe x ) enw i enable write: enables the ckw input (for both non-program and program modes). enr i enable read: enables the ckr input (for both non-program and program modes). ckw i write clock: the rising edge clocks data into the fifo when enw is low; updates half full, almost full, and full flag states. when mr is asserted, ckw writes data into the program register. ckr i read clock: the rising edge clocks data out of the fifo when enr is low; updates the empty and almost empty flag states. when mr is asserted, ckr reads data out of the program register. hf o half full flag: synchronized to ckw. e /f o empty or full flag: e is synchronized to ckr; f is synchronized to ckw. pa f e /xo o dual-mode pin: not cascaded C programmable almost full is synchronized to ckw; programmable almost empty is synchronized to ckr. cascaded C expansion out signal, connected to xi of next device. xi i expansion-in pin: not cascaded C xi is tied to v ss . cascaded C expansion input, connected to xo of previous device. fl /rt i first load/retransmit pin: cascaded C the first device in the daisy chain will have fl tied to v ss ; all other devices will have fl tied to v cc ( figure 1 ). not cascaded C tied to v cc . retransmit function is also available in standalone mode by strobing rt. mr i master reset: resets device to empty condition. non-programming mode: program register is reset to default condition of no parity and pafe active at 16 or less locations from full/empty. programming mode: data present on d 0 - 9,10, or 11 and d 15-17 is written into the programmable register on the rising edge of ckw. program register contents appear on q 0 - 9,10, or 11 and q 15-17 after the rising edge of ckr. oe i output enable for q 0 - 7 , q 9 - 16 , q 8 /pg1/pe1 and q 17 /pg2/pe2 pins. cy7c455 cy7c456 CY7C457 5 electrical characteristics over the operating range 7c455/6/7C 12 7c455/6/7C 14 7c455/6/7C 20 7c455/6/7C 30 parameter description test conditions min. max min. max min. max min. max unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 0.4 v v ih [2] input high voltage 2.2 v cc 2.2 v cc 2.2 v cc 2.2 v cc v v il [2] input low voltage C0.5 0.8 C0.5 0.8 C0.5 0.8 C0.5 0.8 v i ix input leakage current v cc = max. C10 +10 C10 +10 C10 +10 C10 +10 m a i os [3] output short circuit current v cc = max., v out = gnd C90 C90 C90 C90 ma i ozl i ozh output off, high z current oe > v ih , v ss < v o < v cc C10 +10 C10 +10 C10 +10 C10 +10 m a i cc1 [4] operating current v cc = max., i out = 0 ma coml 160 160 140 120 ma ind 180 180 160 140 ma i cc2 [5] operating current v cc = max., i out = 0 ma coml 90 90 90 90 ma ind 100 100 100 100 ma i sb [6] standby current v cc = max., i out = 0 ma coml 40 40 40 40 ma ind 40 40 40 40 ma capacitance [7] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 12 pf ac test loads and waveforms [8, 9, 10, 11, 12] notes: 2. the v ih and v il specifications apply for all inputs except xi . the xi pin is not a ttl input. it is connected to either xo of the previous device or v ss . 3. test no more than one output at a time for not more than one second. 4. input signals switch from 0v to 3v with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum freque ncy (f max ), while data inputs switch at f max /2. outputs are unloaded. 5. input signals switch from 0v to 3v with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 mhz, while the data inputs switch at 10 mhz. outputs are unloaded. 6. all input signals are connected to v cc . all outputs are unloaded. read and write clo cks switch at maximum fr equency (f max ). 7. tested initially and after any design or process changes that may affect these parameters. 8. c l = 30 pf for all ac parameters except for t ohz . 9. c l = 5 pf for t ohz . 10. all ac measurements are referenced to 1.5v except t oe , t olz , and t ohz . 11. t oe and t olz are measured at 100 mv from the steady state. 12. t ohz is measured at +500 mv from v ol and C 500 mv from v oh . 3.0v 5v output r1 500 w r2 333 w c l including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns output 2v equivalent to: th venin equivalent c455-4 200 w all input pulses c455-5 cy7c455 cy7c456 CY7C457 6 switching characteristics over the operating range [13] 7c455/6/7C 12 7c455/6/7C 14 7c455/6/7C 20 7c455/6/7C 30 parameter description min. max. min. max. min. max. min. max. unit t ckw write clock cycle 12 14 20 30 ns t ckr read clock cycle 12 14 20 30 ns t ckh clock high 5 6.5 9 12 ns t ckl clock low 5 6.5 9 12 ns t a data access time 9 10 15 20 ns t oh previous output data hold after read high 0 0 0 0 ns t fh previous flag hold after read/write high 0 0 0 0 ns t sd data set-up 4 5 6 7 ns t hd data hold 0 0 0 0 ns t sen enable set-up 4 5 6 7 ns t hen enable hold 0 0 0 0 ns t oe oe low to output data valid 9 10 15 20 ns t olz [7, 14] oe low to output data in low z 0 0 0 0 ns t ohz [7, 14] oe high to output data in high z 9 10 15 20 ns t pg read high to parity generation 9 10 15 20 ns t pe read high to parity error flag 9 10 15 20 ns t fd flag delay 9 10 15 20 ns t skew1 [15] opposite clock after clock 0 0 0 0 ns t skew2 [16] opposite clock before clock 12 14 20 30 ns t pmr master reset pulse width (mr low) 14 14 20 30 ns t scmr last valid clock low set-up to mr low 0 0 0 0 ns t ohmr data hold from mr low 0 0 0 0 ns t mrr master reset recovery (mr high set-up to first enabled write/read) 12 14 20 30 ns t mrf mr high to flags valid 12 14 20 30 ns t amr mr high to data outputs low 12 14 20 30 ns t smrp program modemr low set-up 12 14 20 30 ns t hmrp program modemr low hold 9 10 15 20 ns t ftp program modewrite high to read high 12 14 20 30 ns t ap program modedata access time 12 14 20 30 ns t ohp program modedata hold time from mr high 0 0 0 0 ns t prt retransmit pulse width 12 14 20 30 ns t rtr retransmit recovery time 12 14 20 30 ns 13. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, and output loading as shown in ac test loads and waveforms and capacitance as in notes 8 and 9, unless otherwise specified. 14. at any given temperature and voltage condition, t olz is greater than t ohz for any given device. 15. t skew1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes of flag update). if the opposite clock occurs less than t skew1 after the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. note : the opposite clock is the signal to which a flag is not synchronized; i.e., ckw is the opposite clock for empty and almost empty flags, ckr is the opposite clock for the almost full, half full, and full flags. the clock is the signal to which a flag is synchronized; i.e., ckw is the clock for the half full, almost full, and full flags, ckr is the clock for em pty and almost empty flags. 16. t skew2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cyc le (for purposes of flag update). if the opposite clock occurs less than t skew2 before the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. see note 15 for definition of clock and opposite clock. cy7c455 cy7c456 CY7C457 7 switching waveforms notes: 17. to only perform reset (no programming), the following criteria must be met: enw or ckw must be inactive while mr is low. 18. to only perform reset (no programming), the following criteria must be met: enr or ckr must be inactive while mr is low. 19. all data outputs (q 0 - 17 ) go low as a result of the rising edge of mr after t amr . 20. in this example, q 0 - 17 will remain valid until t ohmr if either the first read shown did not occur or if the read occurred soon enough such that the valid data was caused by it. write clock timing diagram read clock timing diagram t ckw c455-6 c455-7 t ckh t ckl t hd t sd enabled write disabled write valid data in t sen t hen t sen t hen enabled read disabled read previous word t ckr t ckh t ckl t oh t sen t hen t sen t hen new word t a masterreset (default with free-runningclocks) timing diagram t pmr t mrr t scmr t mrr t ohmr valid data t amr t mrf all data outputs l ow t scmr t mrf hf c455-8 first write t fh t fh t fh t fd t fd t fh t fh t fd t fd t fh d 0 - 17 enw e /f , pafe ,hf q 0 - 17 enr e /f ,pafe ckr ckw mr enw enr q 0 - 17 e /f ,pafe ckr ckw [17, 18, 19, 20] cy7c455 cy7c456 CY7C457 8 switching waveforms (continued) t smrp t mrr t scmr t hmrp t ckh t scmr t ftp t sd t hd t smrp t hmrp t ckh t ap t ohmr t ohp t amr valid data all data outputs l ow last valid read pgm read last word pgm word word 1 word 2 last valid write pgm write first write second write c455-9 master reset (programming mode with free-running clocks) timing dia gram t smrp c455-10 t mrr t scmr t hmrp t ckh t scmr t hen t ftp t smrp t ap t ohmr t ohp t amr valid data pgm word all data outputs l ow last word pgm word word 1 word 2 t ckl t ckw t sen t ckr t ckl t ckh t hen t sen pgm read last valid write pgm write first write second write last valid read t hmrp low low t mrr master reset (programming mode) timing diagram mr enw ckw enr q 0 - 17 ckr mr enw ckw d 0 - 17 q 0 - 17 ckr d 0 - 17 enr pgm word [19, 20] [19, 20] cy7c455 cy7c456 CY7C457 9 notes: 21. count is the number of words in the fifo. 22. the fifo is assumed to be programmed with p>0 (i.e., pafe does not transition at empty or full). 23. r2 is ignored because the fifo is empty (count = 0). it is important to note that r3 is also ignored because w3, the first e nabled write after empty, occurs less than t skew2 before r3. therefore, the fifo still ap pears empty when r3 occurs. because w3 occurs greater than t skew2 before r4, r4 includes w3 in the flag update. 24. ckr is clock and ckw is opposite clock. 25. r3 updates the flag to the empty state by asserting e /f . because w1 occurs greater than t skew1 after r3, r3 does not recognize w1 when updating flag status. but because w1 occurs t skew2 before r4, r4 includes w1 in the flag update and, therefore, updates fifo to almost empty state. it is important to note that r4 is a latent cycle; i.e., it only updates the flag status regardless of the state of enr . it does not change the count or the fifos data outputs. switching waveforms (continued) read to empty timing diagram with free-runningclocks latent cycle t skew1 t skew2 t fd t fd t fd 10 1 0 enabled read flag update enabled read ignored read enabled write ignored read ignored read read enr enw pafe e /f hf c455-11 high low read to empty timing diagram 32 0 1 (no change) t fd t fd r1 enabled flag update 11 0 latent cycle read enabled write t skew2 t skew1 e /f low t fd c455-12 read r2 enabled read r3 enabled read r5 enabled read r4 w1 r1 r2 r3 r4 r5 r6 w1 w2 w4 w5 w6 w3 t skew2 enr ckr enw ckw count count ckr ckw [21, 24, 25] [21, 22, 23, 24] cy7c455 cy7c456 CY7C457 10 notes: 26. the fifo in this example is assumed to be programmed to its default flag values. almost empty is 16 words from empty; almost full is 16 locations from full. 27. r4 only updates the flag status. it does not affect the count because enr is high. 28. when making the transition from almost empty to intermediate, the count must increase by two (16 18; two enabled writes: w2, w3) before a read (r4) can update flags to the less than half full state. switching waveforms (continued) read to almost empty timing diagram with free-running clocks read to almost empty timing diagram with read flag update cycle with free-running clocks t skew1 t skew2 t fd t fd t fd 17 16 18 16 enabled read 17 17 15 enabled write 18 16 t skew2 t fd t fd flag update enabled read enabled read 17 17 15 enabled read read flag update cycle c455-13 c455-14 high high r1 r2 r3 enabled read r4 enabled read r5 enabled read r6 w2 enabled write w3 w4 w1 w5 w6 r2 r3 r4 r5 r6 r7 enabled write w2 enabled write w3 w4 w5 w6 w7 18 (no change) w1 count enr enw e /f pafe hf ckw 17 16 t skew1 t fd enr enw pafe enabled read hf e /f high high r1 w1 count ckr ckr ckw [21, 24, 26] [21, 24, 26, 27, 28] cy7c455 cy7c456 CY7C457 11 notes: 29. ckw is clock and ckr is opposite clock. 30. count = 1,025 indicates half full for the cy7c446 and cy7c456. count = 513 indicates half full for the cy7c447 and CY7C457. count = 257 indicates half full for the cy7c448 and cy7c458. 31. when the fifo contains 1,024 [512] [256] words, the rising edge of the next enabled write causes the hf to be true (low). 32. the hf write flag update cycle does not affect the count because enw is high. it only updates hf to high. 33. when making the transition from half full to less than half full, the count must decrease by two (i.e., 1,025 1,023; two enabled reads: r2 and r3) before a write (w4) can update flags to less than half full. switching waveforms (continued) write to half full timing diagram with free-running clocks 1025 1023 1025 t skew1 t skew2 t fd t fd t fd enabled write enabled write enabled write enabled write enabled read enabled read 1024 1024 1026 c455-15 [513] [512] [511] [512] [513] [514] write to half full timing diagram with write flag update cycle with free-running clocks 1024 1025 1023 1025 t skew1 t skew2 t fd t fd t fd enabled write flag update enabled write enabled write 1024 1024 1026 enabled write enabled read enabled read write flag update cycle [512] [513] [512] [511] [512] [513] [514] pafe c455C16 enw enr hf pafe e /f high high high w1 w2 w3 w4 w5 w6 r1 r4 r5 r6 r3 r2 w1 w2 w3 w4 w5 w6 w7 r1 r4 r5 r6 r2 r3 r7 [257] [256] [255] [256] [257] [258] 1023 [511] [255] (no change) [256] [257] [256] [255] [256] [257] [258] 1024 [512] enr hf e /f high [256] count enw ckw ckr count ckw ckr [21, 29, 30, 31] [21, 29, 30, 31, 32, 33] cy7c455 cy7c456 CY7C457 12 notes: 34. w2 updates the flag to the almost full state by asserting pafe . because r1 occurs greater than t skew1 after w2, w2 does not recognize r1 when updating flag status. w3 includes r2 in the flag update because r2 occurs greater than t skew2 before w3. note that w3 does not have to be enabled to update flags. 35. the dashed lines show w3 as a flag update write rather than an enabled write because enw is high. switching waveforms (continued) write to almost full timingdiagram 2030 2031 2031 2032 t fd t fd t fd enabled write enabled write enabled write enabled write 2032 2031 [1017] 2033 [1017] [1018] [1017] [495] [496] [497] enabled write 2030 [1016] w1 w2 w3 w4 2030 [1016] [494] 2031 [1017] [495] 2032 [1018] [496] enabled read enabled read r1 r2 t skew1 t skew2 t fd low high enw hf pafe enr e /f write to almost full timing diagram with free-runningclocks t skew1 t skew2 t fd t fd t fd enabled write enabled write enabled write enabled write enabled read enabled read c455-17 enw enr pafe hf e /f c455-18 high low w5 w1 w2 w3 w4 w5 w6 r2 r3 r6 r5 r4 r1 [1016] flag update [494] [495] [496] [495] [494] 2031 [1017] [495] 2032 [1018] [496] 2031 [1017] [495] 2030 [1016] [494] 2031 [1017] [495] 2032 [1018] [496] 2033 [1019] [497] count ckw ckr low low count ckw ckr [21, 26, 29] [21, 26, 29, 34, 35] cy7c455 cy7c456 CY7C457 13 note: 36. w2 is ignored because the fifo is full (count = 2,048 [1,024] [512]). it is important to note that w3 is also ignored becaus e r3, the first enabled read after full, occurs less than t skew2 before w3. therefore, the fifo still appears full when w3 occurs. because r3 occurs greater than t skew2 before w4, w4 includes r3 in the flag update. switching waveforms (continued) r1 write to almost full timing diagram with write flag update cycle and free-running clocks 2031 2032 2030 2032 t skew1 t skew2 t fd t fd t fd enabled write flag update enabled write enabled write 2031 2031 2033 c455-19 enabled write enabled read enabled read write flag update cycle [1017] [1018] [1017] [1016] [1017] [1018] [1019] enw enr pafe hf e /f write to full flag timing diagram with free-running clocks t skew1 t skew2 t fd t fd t fd 2047 2048 2047 2048 enabled write enabled write enabled read enw enr pafe e /f hf flag update ignored write c455-20 ignored write ignored write write [1023] [1024] [1023] [1024] latent cycle high low low low w1 w2 w3 w4 w5 w6 w7 r2 r3 r6 r5 r4 r1 r4 r5 r6 r7 r2 r3 w1 w2 w3 w4 w5 w6 2030 [1016] t skew2 [495] [496] [495] [494] [494] (no change) [495] [496] [497] [511] [512] [511] [512] 2048 [1024] [512] count ckw ckr count ckw ckr 2048 [1024] [512] [21, 26, 29] [21, 29, 36] cy7c455 cy7c456 CY7C457 14 notes: 37. in this example, the fifo is assumed to be programmed to generate even parity. the q 0 - 7 word is shown. the example is similar for the q 9-16 word. 38. if q 0 - 7 new word also has an even number of 1s, then pg1 stays low. 39. if q 0 - 7 new word also has odd number of 1s, then pg1 stays high. switching waveforms (continued) even parity generation timing diagram t pg previous word: even number of 1s new word: odd number of 1s ckr q 0 - 7 (q 9 - 16 ) pe 1 ,(pe 2 ) enr enabled read disabled read c455-21 previous word: odd number of 1s new word: even number of 1s enabled read disabled read even parity generationtiming diagram t pg ckr enr c455-22 q 0 - 7 (q 9 - 16 ) pe 1 ,(pe 2 ) [37, 38] [37, 39] cy7c455 cy7c456 CY7C457 15 notes: 40. in this example, the fifo is assumed to be programmed to check for even parity. the q 0-7 word is shown. 41. this example assumes that the time from the ckr rising edge to valid word m+1 > t a . the q 0-7 word is shown. 42. if enr was high around the rising edge of ckr (i.e., read disabled), the valid data at the far right would once again be word m inste ad of word m+1. 43. clocks are free running in this case. 44. the flags may change state during retransmit as a result of the offset of the read and write pointers, but flags will be val id at t rtr . switching waveforms (continued) even par ity checking output enable timing write m c455-23 f 1 read m write m+1 write m+2 word m+ 1: odd number of 1 s word m+ 2: even number of 1 s read m+1 read m+2 t p e t p e 8 lsbs of word m+2 8 lsbs of word m+1 8 lsbs of word m 8 lsbs of word m-1 pe 1 (pe 2 ) enw enr d 0 - 7 q 0 - 7 (q 9 - 16 ) valid da ta word m read m+1 ckr q 0 - 17 oe enr t oh z t o e t ol z valid da ta word m+1 c455C24 l ow word m: even number of 1 s ckw ckr [40] [41, 42] retransmit timing ren/wen fl /rt t prt t rtr 42x5C21 e /f , hf , pafe [43, 44] cy7c455 cy7c456 CY7C457 16 architecture the cy7c455/6/7 consists of an array of 512, 1024, or 2048 words of 18 bits each (implemented by a dual-port array of sram cells), a read pointer, a write pointer, control signals (ckr, ckw, enr , enw , and mr ), and flags (hf , e /f , pafe ). the cy7c455/6/7 also includes the control signals oe , fl , xi , and xo for depth expansion. resetting the fifo upon power-up, the fifo must be reset with a master reset (mr ) cycle. this causes the fifo to enter the empty condition signified by e /f and pafe being low and hf being high. all data outputs (q 0 - 17 ) go low at the rising edge of mr . in order for the fifo to reset to its default state, a falling edge must occur on mr and the user must not read or write while mr is low (unless enr and enw are high or unless the device is being programmed). upon completion of the master reset cy- cle, all data outputs will go low t amr after mr is deasserted. all flags are guaranteed to be valid t mrf after mr is taken high. fifo operation when the enw signal is active (low), data present on the d 0 - 17 pins is written into the fifo on each rising edge of the ckw signal. similarly, when the enr signal is active, data in the fifo memory will be presented on the q 0 - 17 outputs. new data will be presented on each rising edge of ckr while enr is active. enr must set up t sen before ckr for it to be a valid read. enw must occur t sen before ckw for it to be a valid write. an output enable (oe ) pin is provided to three-state the q 0 - 17 outputs when oe is asserted. when oe is enabled (low), data in the output register will be available to the q 0 - 17 outputs after t oe . if devices are cascaded, the oe function will only output data on the fifo that is read enabled. the fifo contains overflow circuitry to disallow additional writes when the fifo is full, and underflow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its q 0C17 outputs even after additional reads occur. programming the cy7c455/6/7 is programmed during a master reset cycle. if mr and enw are low, a rising edge on ckw will write the d 0 - 7,8,or9 and d 15C17 inputs into the programming register [45] . mr must be set up a minimum of t smrp before the program write rising edge and held t hmrp after the program write falling edge. the user has the ability to also perform a program read during the master reset cycle. this will occur at the rising edge of ckr when mr and enr are asserted. the program read must be performed a minimum of t ftp after a program write, and the program word will be available t ap after the read oc- curs. if a program write does not occur, a program read may occur a minimum of t smrp after mr is asserted. this will read the default program value. when free-running clocks are tied to ckw and ckr, program- ming can still occur during a master reset cycle with the adher- ence to a few additional timing parameters. the enable pins must be set-up t sen before the rising edge of ckw or ckr. hold times of t hen must also be met for enw and enr . data present on d 0 - 9 during a program write will determine the distance from empty (full) that the almost empty (almost full) flags will become active. see ta ble 1 for a description of the six possible fifo states. p in ta b l e 1 refers to the decimal equivalent of the binary number represented by d 0 - 7, 8 or 9 . programming options for the cy7c455/6/7 are listed in ta ble 4 . the programmable pafe function on the cy7c455/6/7 is only valid when not cascaded. if the user elects not to program the fifos flags, the default is as follows: the almost empty con- dition (almost full condition) is activated when the fifo con- tains 16 or less words (empty locations). parity is programmed with the d 15 - 17 bits. see tab le 4 for a summary of the various parity programming options. data present on d 15 - 17 during a program write will determine whether the fifo will generate or check even/odd parity for the data present on d 0 - 7 and d 9 - 16 thereafter. if the user elects not to program the fifo, the parity function is disabled. flag operation and parity are described in greater detail in subse- quent sections. flag operation the cy7c455/6/7 provides three status pins when not cas- caded. the three pins, e /f , pafe , and hf , allow decoding of six fifo states ( ta b l e 1 ). pafe is not available when the cy7c455/6/7 is cascaded for depth expansion. all flags are synchronous, meaning that the change of states is relative to one of the clocks (ckr or ckw, as appropriate). [46] the emp- ty and almost empty flag states are exclusively updated by each rising edge of the read clock (ckr ). for example, when the fifo contains 1 word, the next read (rising edge of ckr while enr =low) causes the flag pins to output a state that represents empty. the half full, almost full, and full flag states are updated exclusively by the write clock (ckw). for example, if the CY7C457 contains 2,047 words (2,048 words indicate full for the CY7C457), the next write (rising edge of ckw while enw =low) causes the flag pins to output a state that is decoded as full. since the flags denoting emptiness (empty, almost empty) are only updated by ckr and the flags signifying fullness (half full, almost full, full) are exclusively updated by ckw, careful attention must be given to the flag operation. the user must be aware that if a boundary (empty, almost empty, half full, almost full, or full) is crossed due to an operation from a clock that the flag is not synchronized to (i.e., ckw does not affect empty or almost empty), a flag update cycle is necessary to represent the fifos new state. the signal to which a flag is not synchronized will be referred to as the opposite clock (ckw is opposite clock for empty and almost empty flags; ckr is the opposite clock for half full, almost full, and full flags). until a proper flag update cycle is executed, the syn- chronous flags will not show the new state of the fifo. notes: 45. ckw will write d 0C9 into the programming register. ckr will read d 0C9 during a programming register read. 46. the synchronous architecture guarantees the flags valid for approximately one cycle of the clock they are synchronized to. cy7c455 cy7c456 CY7C457 17 when updating flags, the fifo must make a decision as to whether or not the opposite clock was recognized when a clock updates the flag. for example (when updating the empty flag), if a write occurs at least t skew1 after a read, the write is guar- anteed not to be included when ckr updates the flag. if a write occurs at least t skew2 before a read, the write is guaranteed to be included when ckr updates flag. if a write occurs within t skew1 after or t skew2 before ckr, then the decision of wheth- er or not to include the write when the flag is updated by ckr is arbitrary. the update cycle for non-boundary flags (almost empty, half full, almost full) is different from that used to update the boundary flags (empty, full). both operations are described below. boundary and non-boundary flags boundary flags (empty) the empty flag is synchronized to the ckr signal (i.e., the empty flag can only be updated by a clock pulse on the ckr pin). an empty fifo that is written to will be described with an empty flag state until a rising edge is presented to the ckr pin. when making the transition from empty to almost empty (or empty to less than or equal to half full), a clock cycle on ckr is necessary to update the flags to the current state. in such a state (flags showing empty even though data has been written to the fifo), two read clock cycles are required to read data out of the fifo. the first read serves only to update the flags to the almost empty or less than or equal to half full state, while the second read outputs the data. this first read cycle is known as the latent or flag update cycle because it does not affect the data in the fifo or the count (number of words in fifo). it simply deasserts the empty flag. the flag is updated regardless of the enr state. therefore, the update occurs even when enr is deasserted (high), so that a valid read is not necessary to update the flags to correctly describe the fifo. in this example, the write must occur at least t skew2 before the flag update cycle in order for the fifo to guarantee that the write will be included in the count when ckr updates the flags. when a free-running clock is connected to ckr, the flag is updated each cycle. ta b l e 2 shows an example of a sequence of operations that update the empty flag. boundary flags (full) the full flag is synchronized to the ckw signal (i.e., the full flag can only be updated by a clock pulse on the ckw pin). a full fifo that is read will be described with a full flag until a rising edge is presented to the ckw pin. when making the transition from full to almost full (or full to greater than half full), a clock cycle on ckw is necessary to update the flags to the current state. in such a state (flags showing full even through data has been read from the fifo), two write cycles are required to write data into the fifo. the first write serves only to update the flags to the almost full or greater than half full state, while the second write inputs the data. this first write cycle is known as the latent or flag update cycle because it does not affect the data in the fifo or the count (number of words in the fifo). it simply deasserts the full flag. the flag is updated regardless of the enw state. therefore, the update occurs even when enw is deasserted (high), so that a valid write is not necessary to update the flags to correctly describe the fifo. in this example, the read must occur at least t skew2 before the flag update cycle in order for the fifo to guarantee that the read will be included in the count when ckw updates the flags. when a free-running clock is connected to ckw, the flag updates each cycle. full flag operation is similar to the empty flag operation described in ta b l e 2 . non-boundary flags (almost empty, half full, almost full) the cy7c455/6/7 features programmable almost empty and almost full flags. each flag can be programmed a specific distance from the corresponding boundary flags (empty or full). the flags can be programmed to be activated at the empty or full boundary, or at any distance from the empty/full boundary. when the fifo contains the number of words or fewer for which the flags have been programmed, the pafe flag will be asserted signifying that the fifo is almost empty. when the fifo is within that same number of empty locations from being full, the pafe will also be asserted signifying that the fifo is almost full. the hf flag is decoded to distinguish the states. the default distance from where pafe becomes active to the boundary (empty, full) is 16 words/locations. the almost full and almost empty flags can be programmed so that they are only active at full and empty boundaries. however, the oper- ation will remain consistent with the non-boundary flag opera- tion that is discussed below. . table 1. flag truth table [47] e /f pafe hf state 7c455 words in fifo 7c456 words in fifo 7c457 words in fifo 0 0 1 empty 0 0 0 1 0 1 almost empty 1 => p 1 => p 1 => p 1 1 1 less than or equal to half full p + 1 => 256 p + 1 => 512 p + 1 => 1024 1 1 0 greater than half full 257 => 511 C p 513 => 1023 C p 1025 => 2047 C p 1 0 0 almost full 512 C p => 511 1024 C p => 1023 2048 C p => 2047 0 0 0 full 512 1024 2048 notes: 47. p is the decimal value of the binary number represented by d 0C7 for the cy7c455, d 0C8 for the cy7c456, and d 0C9 for the CY7C457. p = 0 signifies that the almost empty state = empty state. cy7c455 cy7c456 CY7C457 18 almost empty is only updated by ckr while half full and al- most full are updated by ckw. non-boundary flags employ flag update cycles similar to the boundary flag latent cycles in order to update the fifo status. for example, if the fifo just reaches the greater than half full state, and then two words are read from the fifo, a write clock (ckw) will be required to update the flags to the less than half full state. however, unlike the boundary flag latent cycle, the state of the enable pin (enw in this case) affects the operation. therefore, set-up and hold times for the enable pins must be met (t sen and t hen ). if the enable pin is active during the flag update cycle, the count and data are updated in addition to pafe and hf . if the enable pin is not asserted during the flag update cycle, only the flags are updated. ta ble 3 shows an example of a se- quence of operations that update the almost empty and al- most full flags the cy7c455/6/7 also features even or odd parity checking and generation. d 15C17 are used during a program write to describe the parity option desired. ta b l e 4 summarizes pro- grammable parity options. if the user elects not to program the device, then parity is disabled. parity information is pro- vided on two multi-mode output pins (q 8 /pg1/pe1 and q 17 /pg2/pe2 ). the three possible modes are described in the following paragraphs. programmable parity parity disabled (q 8 /q 17 mode) when parity is disabled (or the user does not program parity option) the fifo stores all 18 bits present on d 0C17 inputs internally and will output all 18 bits on q 0C17 . parity generate (pg mode) this mode is used to generate either even or odd parity (as programmed) from d 0C7 and d 9C16 . d 8 and d 17 inputs are ignored. the parity bits are stored internally as d 8 and d 17 , and during a subsequent read will be available on the pg1 and pg2 pins along with the data words from which the parity was generated (q 0C7 and q 9C16 ). for example, if par- ity generate is set to odd and the d 0C7 inputs have an even number of 1s, pg1 will be high. parity check (pe mode) if the fifo is programmed for parity checking, it will compare the parity of d 0C8 and d 9C17 with the program register. for example, d 8 and d 17 will be set according to the result of the parity check on each word. when these words are later read, pe 1 and pe 2 will reflect the result of the parity check. if a parity error occurs in d 0C8 , d 8 will be set low internally. when this word is later read, pe 1 will be low. retransmit the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. the retransmit (rt ) input is active in the standalone and width expansion modes. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have occurred since the last mr cycle. a low pulse on rt resets the internal read pointer to the first physical location of the fifo. wclk and rclk may be free running but must be disabled during and t rtr after the retransmit pulse. with every valid read cycle after retransmit, previously accessed data is read and the read point- er is incremented until it is equal to the write pointer. flags are gov- erned by the relative locations of the read and write pointers and are updated during a retransmit cycle. data written to the fifo after ac- tivation of rt are transmitted also. the full depth of the fifo can be repeatedly retransmitted. table 2. empty flag (boundary flag) operation example status before operation status after operation current state of fifo e /f afe hf number of words in fifo operation next state of fifo e /f afe hf number of words in fifo comments empty 0 0 1 0 write (enw = 0) empty 0 0 1 1 write empty 0 0 1 1 write (enw = 0) empty 0 0 1 2 write empty 0 0 1 2 read (enr = x) ae 1 0 1 2 flag update ae 1 0 1 2 read (enr = 0) ae 1 0 1 1 read ae 1 0 1 1 read (enr = 0) empty 0 0 1 0 read (transition from almost empty to empty) empty 0 0 1 0 write (enr = 0) empty 0 0 1 1 write empty 1 0 1 1 read (enr = x) ae 1 0 1 1 flag update ae 1 0 1 1 read (enr = 0) empty 0 0 1 0 read (transition from almost empty to empty) cy7c455 cy7c456 CY7C457 19 width expansion modes during width expansion all flags (programmable and nonpro- grammable) are available. these fifos can be expanded in width to provide word width greater than 18 in increments of 18. during width expansion mode all control line inputs are common. when the fifo is being read near the empty (full) boundary, it is important to note that both sets of flags should be checked to see if they have been updated to the not empty (not full) condition to insure that the next read (write) will per- form the same operation on all devices. checking all sets of flags is critical so that data is not read from the fifos staggered by one clock cycle. this situation could occur when the first write to an empty fifo and a read are very close together. if the read occurs less than t skew2 after the first write to two width-expanded devices, a and b, device a may go almost empty (read recognized as flag update) while device b stays empty (read ignored). this occurs be- cause a read can be either recognized or ignored if it oc- curs within t skew2 of a write. the next read cycle outputs the first half of the first word on device a while device b updates its flags to almost empty. subsequent reads will continue to output staggered data assuming more data has been written to fifos. depth expansion mode the cy7c455/6/7 can operate up to 83.3 mhz when cascad- ed. depth expansion is accomplished by connecting expan- sion out (xo ) of the first device to expansion in (xi ) of the next device, with xo of the last device connected to xi of the first device. the first device has its first load pin (fl ) tied to v ss while all other devices must have this pin tied to v cc . the first device will be the first to be write and read enabled after a master reset. proper operation also requires that all cascaded devices have common ckw, ckr, enw , enr , d 0C17 , q 0C17 , and mr pins. when cascaded, one device at a time w ill be read enabled so as to avoid bus contention. by asserting xo when ap- propriate, the currently enabled fifo alerts the next fifo that it should be enabled. the next rising edge on ckr puts q 0C17 outputs of the first device into a high-impedance state. this occurs regardless of the state of enr or the next fifos empty flag. therefore, if the next fifo is empty or undergoing a latent cycle, the q 0C17 bus will be in a high-im- pedance state until the next device receives its first read, which brings its data to the q 0C17 bus. program write/read of cascaded devices programming of cascaded fifos is the same as for a single device. because the controls of the fifos are in parallel when cascaded, they all get programmed the same. during program mode, only parity is programmed since almost full and almost empty flags are not available when cy7c455/6/7 is cascaded. only the first device (fifo with fl =low) will output its pro- gram register contents on q 0C7 during a program read. q 0C17 of all other devices will remain in a high-impedance state to avoid bus contention. figure 1. depth expansion with cy7c455/6/7 data in data out d 0C 17 ckw enw q 0C 17 ckr enr mr q 0C 17 d 0C 17 mr pafe/xo xi v cc v ss hf e/f fl/rt cy7c455,6,7 ckw ckr enr enw oe full empty d 0C 17 ckw enw q 0C 17 ckr enr mr pafe/xo xi hf e/f fl/rt cy7c455,6,7 oe c455-25 cy7c455 cy7c456 CY7C457 20 table 3. almost empty flag (non-boundary flag) operation example [48] status before operation status after operation current state of fifo e /f afe hf number of words in fifo operation next state of fifo e /f pa f e hf number of words in fifo comments ae 1 0 1 32 write (enw = 0) ae 1 0 1 33 write ae 1 0 1 33 write (enw = 0) ae 1 0 1 34 write ae 1 0 1 34 read (enr = 0) cy7c455 cy7c456 CY7C457 ? cypress semiconductor corporation, 1997. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams 52-lead plastic leaded chip carrier j69 52-lead plastic quad flatpack n52 |
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